1. Field of Invention
The present invention relates to a method for manufacturing a memory. More particularly, the present invention relates to a method for manufacturing a non-volatile memory.
2. Description of Related Art
Non-volatile memory can be used to perform storage operation, read operation and erasing operation for several times. The non-volatile memory possesses the ability that the stored data still remained in the memory even after the power is off. Furthermore, the non-volatile memory also has the properties such as high access rate, light in weight but large in memory capacity and small equipment volume. Therefore, the non-volatile memory becomes the most widely used memory device in the personal computers and the electronic equipments.
The floating gate and the control gate of the common non-volatile memory are made of doped polysilicon. FIGS. 1A through 1C are cross-sectional views showing a conventional method for forming a non-volatile memory. As shown in FIG. 1A, isolation structures 110 are formed in a substrate 100. A tunneling dielectric layer 120, a doped polysilicon layer 130 and a mask layer 135 are formed over the substrate 100 sequentially. The mask layer 135 is used to pattern the underlay doped polysilicon layer 130.
As shown in FIG. 1B, a patterned photoresist layer (not shown) is formed on the mask layer 135. By using the patterned photoresist layer as a mask, the pattern of the patterned photoresist layer is transferred onto the mask layer 135. Then, by using the patterned mask layer 135 as a mask, the doped polysilicon layer 130 is etched.
As shown in FIG. 1B together with FIG. 1C, the patterned mask layer 135 is removed. A gate dielectric layer 140 is formed over the substrate 100. Thereafter, another doped polysilicon layer 150 is formed on the gate dielectric layer 140. Then, the doped polysilicon layer 150 and the doped polysilicon layer 130 are defined to be a control gate (doped polysilicon layer 150) and a floating gate (doped polysilicon layer 130).
In the aforementioned method for forming the non-volatile memory, a doped polysilicon layer 130 is formed over the substrate 100 first and then a photo lithography process is performed to pattern the doped polysilicon layer 130. The cost of the aforementioned photo lithography process is high and it is not easy to control the photo lithography process. That is, the misalignment issue easily happens.
As the process of the integrated circuit is below 90 nm, the line width of the device is smaller and smaller. On the other words, the width of the isolation structure 110 is narrower. Under the circumstance mentioned above, the process window of the photo lithography process is decreased so that the tolerance range for the misalignment is decreased as well. If the substrate 100 is exposed during the etching process, the abnormal conduction between the devices will happen. Therefore, the yield of the device is affected.
Moreover, with the decreasing of the line width of the device, the gate electrode coupling between the floating gate and the control gate is decreased. Accordingly, the operating voltage of the non-volatile memory is inevitably increased. Hence, it is disadvantage to apply the non-volatile memory onto the portable electronic product having highly demands on low power consumption. Therefore, how to improve the process window of the non-volatile memory, to prevent the memory from being abnormally connected and to manufacture a memory having high gate electrode coupling becomes a very important task.